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Design And Implementation Of FPGA Prototype For MP3 Audio Decoder

Posted on:2010-08-14Degree:MasterType:Thesis
Country:ChinaCandidate:F H DuFull Text:PDF
GTID:2178360275978158Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Nowadays MPEG Audio Layer3 (MP3) has become one of the most popular music for its high music quality, low data complexity and high compression rate, and it is widely used in Internet and portable devices. So we focused on the MPEG-1 MP3 audio decoder, studied the hardware architecture to meet the real time requirement and to minimize the cost, implemented the prototype chip on FPGA and evaluated the performance of the MP3 decoder prototype.The main contributions of this thesis are as follows:(1) Algorithms are merged to reduce the hardware cost and improve the processing speed. Several decoding steps are joined together using hardware sharing techniques. For example, the reordering is merged into the re-quantizing step, so the number of memory accessing is reduced by half. And in IMDCT block three steps are integrated together, thus the memory buffers between the steps for storing temporary data can be eliminated.(2) New hardware architecture is proposed in several modules of MP3 decoder. In re-quantizing and stereo modules, pipeline strategy is applied and the length of combinational logic is shortened by inserting registers to improve the performance and reliability of the decoder. By using the continually accessing techniques to shared RAM, computing operation is hided behind the memory accessing. By fully utilizing the zero area feature of the frequency line, the complexity of data computation is minimized and the processing speed is accelerated.(3) The prototype chip of MP3 audio decoder is designed and implemented in FPGA. The chip is first modeled in Register Transfer Level (RTL) in Verilog HDL, and then verified for functionality with simulation tool, and at last implemented on FPGA platform of Stratix II EP2S180. The utilization of the FPGA resources is about 5%, in that ALUTs are 7189 and the registers are 4024. The maximum frequency can reach up to 69.6MHz. Experiment result showed that FPGA prototype for MP3 audio decoder can play the music successfully and the audio quality is quite well.
Keywords/Search Tags:MP3 decoder, FPGA, Verilog HDL, hardware design
PDF Full Text Request
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