Design And Implementation Of FPGA Prototype For MPEG-2 AAC Audio Decoder

MPEG-2 Advanced Audio Coding (AAC) is a very flexible coding standard, which supports 48 main channels, 16 low-frequency channels and its compression ratio is up to 11:1. More ever, the quality of AAC can still be Hi-Fi, when the bit rate reaches 64kbps. Comparing to MPEG Layer 3, AAC only needs 70% bit rate to maintain the same audio quality. So it is widely used in DVD-Audio, mobile communication, network phone and online radio. In this essay, An MPEG-2 AAC decoder is designed and verified using FPGA. Serial and parallel models of system-level architecture are firstly established. Then the MPEG-2 AAC audio decoder prototype chip was designed and implemented in FPGA.The contribution of the essay is summarized as follows:(1) The system-level models of MPEG-2 AAC decoder were evaluated. A hardware implementation solution of AAC FPGA prototype was proposed considerating the power, area and flexibility. Parallel and serial architectures are proposed. The parallel architecture was implemented because it can be easily extended to multi-channel in the future.(2) The hardware circuits of several main modules were designed, which mainly focused on the implementation and optimization of Prediction and TNS modules. Pipelined method was adopted in Prediction module, which compressed the prediction result rate to one per 30-clock cycles. The float division was implemented by using multiplication based on look up tables. In TNS module, serial and parallel architectures of IIR filter were proposed. For the consideration of simplifying the control logic, serial architecture was implemented.(3) The MPEG-2 AAC decoder prototype was implemented. The chip was implemented using Verilog HDL, and run on SatrixII EP2S180 develop board. The total resource occupied is 24116 ALUTs, 18917 registers and 3397960 memory bits. The audio quality of the decoder is good by using stereo audio codec on the board.