Design And FPGA Implementation Of Polar Code Decoder Based On Successive Cancellation Decoding Algorithm

In digital communication system,information will be interfered by many factors during transmission,which will lead to information distortion.In order to reduce the error rate of information during transmission,the related technologies must be studied to deal with such problems.Error correction code has been developed for many years.Many professional scholars have proposed various coding schemes,some of which perform well.However,these coding schemes have not realized that the channel capacity can be achieved in Shannon theory until the emergence of polar codes changed this situation.Polar code is the only channel coding that can prove to reach Shannon limit under ideal conditions,which performance will decay exponentially with the increasing of packet length.Polar code is a new coding technology proposed by Turkish professor E.Arikan.Polar code has a specific coding and decoding structure like other channel coding.Meanwhile,polar code uses channel polarization to complete the encoding and decoding.Nowadays,polar code has been applied in various industries.In the 5G short code scheme of the 87th(3rd Generation Partnership Project,3GPP)meeting,Huawei defeated its competitors and determined the polar code as the coding scheme of 5G Enhanced Mobile Broadband(e MBB)control channel.This thesis takes polar code in 5G standard as the research object.The development trend and research status of Polar code are briefly introduced firstly,and channel reliability analysis is performed in different channels.Then,the encoding of Polar code is described.The encoding process of Polar code is studied and encoding examples are given to explain.In terms of decoding,this thesis focuses on the Successive Cancellation(SC)decoding algorithm of polar code,Successive Cancellation List(SCL)decoding algorithm,Cyclic Redundancy Check(CRC)aided decoding algorithm,and Belief Propagation(BP)decoding algorithm.In this thesis,the MATLAB software is used for performance simulation,and the influence of packet length and code rate on decoding is analyzed through simulation results.At the same time,the SC and SCL algorithms of Polar were compared with the Sum-Product Algorithm(SPA)of Low-Density Parity Code(LDPC)code.Compared with the SPA decoding algorithm of LDPC codes,the performance of the SCL decoding algorithm with a list number of 8 is increased by about 0.1d B when the Bit Error Rate(BER)is 10-4 and packet length N is 256.Meanwhile,the performance of polar code and LDPC code is superior to the performance of convolutional codes.The SPA decoding algorithm of the LDPC code and the SCL decoding algorithm with list number of 4 show almost the same Packet Error Rate(PER)performance(the difference is no more than 0.1d B)When the PER is 10-3.Under the condition of code length N=512 and BER=10-4,the SCL decoding algorithm with list number of 2 has decoding performance like that of SPA decoding algorithm(with difference is no more than 0.1d B).And under the same BER(BER=10-4)condition,the SCL decoding algorithm with list number of 4 is increased by about 0.25 d B compared with the SPA decoding algorithm.In addition,compared with the SPA decoding algorithm of LDPC codes,the performance gain of the SCL decoding algorithm with list number of 2 is about 0.3d B when the PER is 10-3.After discussing the decoding algorithms of Polar codes and performing simulation,we choose the SC decoding algorithm which is suitable for FPGA hardware implementation.This thesis designs the decoder hardware structure and each sub-module inside the decoder,and summarizes the design process of the SC decoder hardware structure.Each module is introduced in detail,including the design of two decoding nodes,PE calculation module and LLR decision module.In the end,the Verilog Hardware Description Language(HDL)is used to implement the programming of each module of decoder in the Quartus II software of EDA.