Design Of Variable Length Decoder For AVS And Implementation On FPGA

With the development of information technology, multimedia, digital information and communication technology, the demand of multimedia video compression technology have increased rapidly. AVS - As the first audio and video codec standard of china which has the independent intellectual property rights come into being. AVS is the second generation of source coding standards with independent intellectual property rights of china, and is the abbreviation of "technologically advanced audio and video information coding" series standard. By the end of February 2006, AVS standard was officially approved to be the digital audio and video national standard, and formally implemented from March 1, 2006. Compared with the most advanced video coding standard H.264 the complexity of AVS has decreased apparently while achieving the same compression performance. Therefore do research on AVS video codec is a strong support of the Chinese video coding standard which has the independent intellectual property rights.The complexity of AVS video coding standard is lower than H.264, but using the software decoder is still difficult to achieve real-time decoding. The reason is that the software decoder decodes the bitstream almost by order, and its functional modules work in succession; but the most prominent advantage of hardware decoder is that each module works parallel, so the hardware decoder can solve the real-time decoding problems. The design of variable length decoder in this paper is an important function module of the AVS hardware decoder. The variable length decoder is located at the first level of the decoder, so its speed of decoding determines the speed of the whole decoder. Therefore based on this character of VLD,my paper using FIFO appropriately to make the structure parallel and minimizing the sub-modules running rhythms of VLD, making the operating speed of the whole system enhance greatly. The design has been verified on the FPGA platform, and the result shows that the design can meet the real-time decoding of the AVS standard definition video.The design of VLD which support the AVS standard has the features as follows:(1) At the functional aspects: Support the AVS standard, be able to complete the AVS standard variable length decoding;(2)At the structural aspects: the appropriate using of FIFO make the functional modules of entire variable length decoding can work in parallel; (3) At the storage space aspects: At the premise of decoding correctly, save the using of FPGA memory space as far as possible;(4) At the decoding speed aspects: Because of the appropriately adding FIFOs to the architecture, the function modules of VLD can work parallel, improving the decoding speed.This paper does a deep research on the entropy codec algorithm of AVS video standard and the hardware system development process.In study and development process, the main jobs are as follows:(1) Analyze the AVS standard and do research on the VLD of AVS, find the best methods of implementation.(2) Make division of the function module according to the character of the variable length code of AVS. Work out the entire structure diagram.(3) Design the sub-module and describe it with Verilog Hardware language, and then do the simulation and verification of each module.(4) Do the united debugging simulation and verification of all the sub-modules, and then compare the validation results with the results of rm52j which is the standard C code of AVS, in the end,test if the results are correct and the function is integrity.(5) Do the united debugging of the VLD and other modules of AVS decoder.(6) Verify the VLD of AVS on the FPGA platform.(7) Combine the VLD and other modules of AVS and verify them on the FPGA platform.