Voice Decoder Chip Design And Fpga Hardware

The ASIC chip of speech decoder is designed in this paper. It consists oftwo cells: the one is decompression process cell from the digital signal ofAdaptive Differential Pulse Code Modulation (ADPCM) to the digital signalof Pulse Code Modulation (PCM); and the other is speech synthesis outputusing PWM, which adopts Pulse Width Modulation (PWM) technology so asto turn digital speech information of PCM into pulse width modulation wave,then output using speaker. In the paper, the designing method , function and principle of VHDLdesign is introduced briefly, the basic principle and FPGA technology also beexplained.