Logic Synthesis And Equivalence Checking Of Communication Chip

Along with the development of IC, it's more and more difficult to design the circuit, thus, SoC (System on Chip) has being a development direction of microelectronics. In the substance related above, one of the core technologies is the design of IP core and the reuse technology. The development of IC and the importance of SoC and IP reuse technology are been researched. The back-end technology upon the SoC communication chip with IP core is discussed.The main thesis involves: The formulation of strategy in logic synthesis and the constraint in synthesis design of system chip,include area constraint and timing constraint;To assure the validity of design, which is the key issue of IC, formal verification was lead into the design. According to the theory of formal verification, it use equivalence checking to assure the validity of back-end design; According to the theory of time analysis and with the successful simulation of static time analysis under all kinds of modes, the chip can be put into tape-out successfully.During the process of logic synthesis, Talus Design produced by Magma was used, and Onespin EC by Onespin was used for equivalence checking. Further more, Prime Time by Design Compiler was used for static time analysis. The project was put into tape-out by Infineon in November, 2008.