Design Of Scan Chain Security Circuit Based On SDSFF Latch

With the continuous development of semiconductor technology,cryptographic chips are increasingly being applied to various scenarios in the field of information protection.The security of the crypto chip itself is closely related to the key.Therefore,the development of a security circuit that protects the cryptographic chip key is an important part of chip security.The introduction of design for testability has significantly improved the yield of chips.Can greatly improve the controllability and observability of the chip.But the attacker will also use the scan design to snoop on the internal logic of the cryptographic chip to get the key.Therefore,this design for testability brings potential risks.The demand for non-intrusive defense technologies based on scan chains is increasing.In order to solve the security problem of cryptographic chips caused by testability,this paper takes AES(Advanced Encryption Standard)cryptographic chips as the research object,analyzes the encryption method of AES cryptographic chips and the process of obtaining AES chip keys through differential attacks,and then passes Based on the analysis of the security defense defects of the static double feedback XOR scan chain,the XOR double feedback dynamic obfuscation safety scan circuit based on the combination of SDSFF(State Dependent Scan Flip-Flop)latch and PUF(Physical Unclonable Function)is designed,including dynamic obfuscation circuit,PUF random circuit,authentication circuit,status update circuit and control circuit.Among them,the PUF random circuit compares the two through the NAND-type latch(which can identify the difference of input signal from'0'to'1')and the NOR type latch(which can identify the difference of input signal from'1'to'0')as an arbiter The output delay difference between D flip-flops is used to construct a PUF circuit to output random data.The design of the dynamic obfuscation circuit is to add a two-to-one selector to the scan chain of the AES cipher chip,and the output of the double feedback XOR circuit,inverter or the previous scan flip-flop is dynamically selected through the selector to realize the obfuscated data.A total of 127selectors are placed between the scanning units.The control ports of these 127 selectors are the 127-bit random data output by the PUF random circuit and the 127-bit data based on the output of the SDSFF latch in the dynamic confusion circuit and the 127-bit authentication circuit shift chain output data through exclusive OR The doors are connected together for common control.The dynamics of the dynamic confusion circuit comes from the output based on the SDSFF latch.The state update circuit controls the latch by matching the preset KEY value(selected as'011'in this article)with the output state of the flip-flops at different positions on the scan chain circuit Loading.Once the KEY value matches successfully,the state update circuit controls 127 latches to load the output data of the scan unit flip-flop.The randomness of the dynamic confusion circuit comes from the PUF random circuit.The PUF random circuit continuously transmits random data to the dynamic confusion circuit through a clock trigger.Through analysis,it is concluded that the dynamic obfuscation circuit adds dynamics and randomness,which can reduce the possibility of an attacker to analyze the key through the scan chain to(₌₁¹²⁷(₁₂₇?2))^-1,which improves safety.This article introduces the authentication mechanism of LK lock and key into the security scanning circuit designed in this article.When the chip needs to be tested,it must be tested and authenticated first.Only when the correct test authentication key is input,the tester can perform the chip test normally.The authentication circuit will output a control signal to control the selector in the dynamic confusion circuit to select the input of the'1'signal,and the chip can be performed normally test.When the wrong test authentication key is input,the dynamic obfuscation circuit will output dynamic random data so that the attacker cannot obtain effective information through analysis.In order to verify the safety and testability of the proposed scheme.The security scan chain is inserted on the AES crypto chip,and the scan chain test circuit and test vector are generated based on SDSFF and PUF.The cost of the security design scheme designed in this paper accounts for 1.01%of the AES crypto chip circuit,and it can defend against mode switching attacks,test mode attacks,and reset/set attacks.