Research On Area Effective Scan Chain Insertion Approaches For FPGA Hardware Emulation Platform

FPGA-based hardware emulation platform has been widely used for IC functional verification as it runs significantly faster than software simulation.However,the controllability and observability of circuit internal signals mapped onto FPGA are restricted,which poses challenges for verification engineers.Scan chains provide full controllability and observability of the circuit states on FPGA,at a cost of large area overhead.Our efforts to reduce the area overhead of scan chain involve the following three aspects.First,a cost effective scan chain insertion approach based on logic fusion is proposed.The approach utilizes configured but partially used LUTs to implement the logic needed by scan chain,which improves the efficiency of LUTs.Logic fusion can be used on different FPGA platforms to implement both full scan and partial scan.Experiments show that proposed logic fusion approach reduces the logic overhead by 22.9% averagely compared with primitive replacement approach in full scan circumstance.Second,to further reduce the overhead of scan insertion,BALLAST partial scan methodology has been researched.Based on the BALLAST methodology,we proposed an integer linear programming(ILP)model for balanced structure based partial scan problem.Combining the two stages into one,the proposed ILP model overcomes the disadvantages of BALLAST approach and introduces a theoretically global optimal solution of balanced structure partial scan problem based on the graph model proposed in BALLAST.We show that the ILP model plus logic fusion results a LUTs reduction by 13.5% averagely compared with BALLAST partial scan.Third,detailed analysis on balanced structure shows that the graph model used by BALLAST approach presents an obstacle to reducing scan flip-flop number.Consequently,we propose using the extended sequential graph model to formulate the balanced structure partial scan problem.Experiments show that extended graph model based approach reduces the logic overhead by 17.9% averagely compared with BALLAST.In conclusion,all the three methods focus on reducing logic overhead of scan chain on FPGA platform.