Research And Design On Reconfigurable Cache For Multimedia Computation

Recently, multimedia computing is a dominating workload in the research field of computer science. It is applicable to production and living widely in embedded systems. Multimedia computing normally has large data sets and various data types, therefore, the behavior of memory system has a strong effect on the performance. As the embeded devices'ability of power supplying is strictly limited by size and weight, it is necessary to research on performance and power consumption in memory architecture which supports multimedia computing. As the bridge between processor and memory, Cache plays an important role, meanwhile it occupies large chip area and becomes the main source of the energy consumption. In the interests of high performance and low power consumption in memory architecture, three kinds of Cache models have been proposed, which use the reconfiguration strategy based on the requirements of the multimedia system.TBLRC is a line-reconfigurable Cache based on time slice. Most of the multimedia applications use block-partitioning algorithms in which large input files are divided into small blocks, and the divided blocks have good spatial locality. The strategy dynamically changes replacing line size to adapt to the size of the data block through observing the reference flags of adjacent base lines. So it can make full use of the spatial locality to reduce Cache miss rate and improve the efficiency of data pefetch.TBWRC is a way-reconfigurable Cache based on time slice. When the associativities increase, the decrease of conflict miss will reduce Cache miss rate, however SRAM accesses will consume more dynamic energy because of the complexity of the control circuit. TBWRC dynamically changes the associativities of Cache through analyzing the characteristics of different program phases in order to reduce dynamic energy significantly with small performance degradation. In TBWRC, a self-tuning threshold algorithm has been proposed. Through recording the hit count of Least Way and Extra Way, it can provide judgement for way-reconfiguration. The accuracy of reconfiguration in TBWRC is better than Search Heuristics in the contrasting model.TBLAWRC is a line and way reconfigurable Cache based on time slice. It combines the characteristics of TBLRC and TBWRC effectively, and it dynamically changes the associativities and the size of replacing lines through the modification of Cache address mapping rule and coordination of reconfiguration state machine. Compared with the two former models, it can optimize both of performance and power consumption.