Research And Design Of Low-power Reconfigurable Cache In Embeded System

In recent years, the energy consumption has become the focus of the embeddedsystem design, mainly due to the widely use of the portable and mobile embeddeddevices with limited battery capacities. The main role of cache is to bridge the speedgap between the main memory and CPU. By leveraging the locality in both temporaland spatial space, data can be pre-fetched from main memory into cache, so that CPUcan access them in cache instead of much slower main memory, which can reduce theaccessing time dramatically. The design of cache has great impacts over theperformance of a computer system. At the same time, cache also takes a significantportion of CPU’s total power consumptions. As the result, it is critical important tostudy the novel architectures of cache, making a reasonable trade-off between theperformance and power comsumptions.The thesis first surveys the recent advances over the low-power cache designtechniques. Then proposes two dynamic reconfigurable schemes for low-power cacheusing dynamic reconfigurable techniques: one is based on the branch-instructionfrequency (BRDRC), and the other is based on the instruction-cycle(IC-DRC).Thedynamic reconfigurable techniques mean that the cache configurations can beadjusted dynamically according to the runtime demandings of applications tominimize the power consumptions as well as the performance loss.The BRDRC algorithm uses the branch-instruction frequency to detect phasechanges and determine the time to adjust cache configuration. In each phase, the statemachine uses the dynamic configurable strategy to govern cache and adjust cache’sassociativity, and then check the new miss rate to obtain the optimal configuration ofcache. Compared with previous work, the BRDRC algorithm not only saves morepower dissipation, but also greatly reduces the hardware overhead.The IC-DRC algorithm is an improvement of BRDRC. It uses theinstruction-cycle to detect phase changes. In each phase, the state machine uses theaverage access time to predict the cache access and obtain optimal configuration. Theprediction mechanism could not only avoid the unnecessary reconfigurations, but alsoreduce the performance loss. At the same time, the parameters of the average accesstime could have better influence in performance than the miss rate. The experimentalresults show that the IC-DRC algorithm significantly reduces the performance loss, and further saves the energy consumption compared to the BRDRC algorithm andprevious works.