Reconfigurable On-Chip Memory Architecture For Low Power Embedded System

Embedded system is the core of intelligent portable electronic devices.In battery-powered application scenarios such as mobile terminals and computing nodes of the Internet of Things,how to reduce power consumption and prolong the battery life of devices has become a research focus of researchers.As a key component of embedded microprocessor,on-chip memory increases with the improvement of system performance,and its power consumption has become one of the important factors restricting the further improvement of embedded system performance.Therefore,the low power design of on-chip memory is of great significance.Based on the in-depth analysis of the structure of on-chip memory and the operation characteristics of access instruction in embedded microprocessor,aiming at the problem of power redundancy in access operation of Cache structure,an on-chip memory structure with switchable memory mode was proposed.The structure can configure the on-chip memory unit to work in Cache mode and SRAM mode.According to the running characteristics of the program,the Cache can be reconstructed into on-chip SRAM by configuring the reconfiguration control register,and then reduce the power consumption of the Cache redundancy structure by means of clock gating.Firstly,a four-level pipeline processor based on RV32IM instruction set and supporting instruction Cache and data Cache is constructed as the basis of reconfigurable memory structure design.Secondly,the reconfigurable memory control structure and power consumption control structure are designed respectively for instruction memory and data memory,and the hardware and software co-configuration is realized.Finally,the Design Compiler tool was used to logic synthesize the overall Design in UMC110nm process,and Comparing the values of the general register and data momery in the actual processor with the theoretical values to verify the correctness of the reconfigurable memory structure and function.The power consumption of the on-chip reconfigurable memory structure is tested by using the Primetime-PX tool and various benchmarks,and the influence of different memory reconfiguration on processor energy consumption is analyzed.The test results show that in low power memory mode,the power consumption of instruction Cache decreases by 60%and that of data Cache decreases by 50%,among which the power consumption control effect of Cache memory is the most significant.The energy consumption of the entire processor decreases with the increase of the ratio of low-power programs and the decrease of the number of reconstructions.When the ratio of low-power programs is 90%,the power consumption of the entire processor decreases by 68.3%.In this paper,the reconfiguration control introduces 3.6%additional area overhead and 3%additional power consumption overhead.Low power reconfigurable memory architecture can reduce the power consumption of the whole system without affecting the performance of the processor.