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Design And Test Of CAN Bus Controller Based On Verilog HDL

Posted on:2010-02-12Degree:MasterType:Thesis
Country:ChinaCandidate:S J DuanFull Text:PDF
GTID:2178360272996602Subject:Microelectronics and Solid State Electronics
Abstract/Summary:
The Controller Area Network (CAN) developed by Bosch in the early 1980s is a serial bus in order to figure out the data exchange between controllers and testing instruments in modern automobile. It defines a standard for the efficient and reliable communication between sensors or actuators, controllers, and other nodes in real-time applications. CAN is the standard existence in a large variety of networked embedded control systems. The early CAN development was mainly supported by the vehicle industry. It is set up in a variety of passenger cars, trucks, boats, spacecraft, and other types of transportation. The protocol is also widely apply to industrial automation and other fields of networked embedded control today, with applications in different products such as medical equipment, weaving machines, production machinery, building automation, and wheelchairs.In the first chapter of the thesis, It mainly introduces something about the concepts and the history of CAN bus, the composition of CAN bus nodes and the characteristics of CAN bus. Then It refers about the current situation of CAN bus mainly from four aspects: firstly, the improvement of the existing protocol, putting forward new protocol and standardization; secondly,the design of CAN bus chips about the controller chip or transceiver chip; thirdly, the application of CAN bus research; fourthly, the development of the ECU (Electronic Control Unit) based on CAN bus. At the end of the first chapter it introduced the research significance of the thesis based on the conclusion of CAN bus research state. Finally it specifies about the composition of this paper.The second chapter of the thesis it is devoted to account for the specification of the CAN bus. It explains about the development of the communication protocol simply for introduce of the CAN bus protocol. After that it refers the communication model of CAN bus and compares with the ISO/OSI network model. Then it analyzes CAN bus protocol with the physical layer and the data link layer. In the physical layer, it introduces bit representation, dominant and recessive bits, bit timing and synchronization, bit rate and bus length. In the data link layer, it introduces CAN messages, bus arbitration and error limitation.In the third chapter of the thesis, it designs a controller of CAN-bus using Verilog HDL. It develops the design process of the CAN bus controller at first. And then it analyzes the function of a CAN-bus controller SJA1000, which is made by PHILIPS, and designs the function block diagram of the CAN bus controller. The function of CAN bus controller module consists of three parts: CAN_IML, CAN_registers and CAN_core. It main introduces CAN_registers and CAN_core. CAN_core comprises bit- stream process, bit-timing logic and the clock divider.In the forth chapter of the thesis, it designs a CAN bus controller simulation test. First it introduces the process of testing digital circuits so as to arrive at our own design process. Then it introduces the CAN bus controller software simulation. Finally it designs a CAN-bus node based on the FPGA-based CAN bus controller. I use it to do a communication test with a CAN-bus node based on SJA1000 and test verifies the correctness of the design.
Keywords/Search Tags:CAN bus, Controller, FPGA, Verilog HDL
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