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Design And Verification Of On-chip CAN-bus Controller For MIPS Processor

Posted on:2018-11-01Degree:MasterType:Thesis
Country:ChinaCandidate:H ChenFull Text:PDF
GTID:2348330542451508Subject:Integrated circuit engineering
Abstract/Summary:
The Control Area Networks(CAN)is one of the serial data bus which is the best application prospect in the modern industrial system.It is used commonly in automobile data transfer and interaction between industrial instruments.The cars communicate between discrete digital devices because of its timely delivery,flexible configuration,high reliability,high transmission rate characeristic.A CAN2.0A Bus controller IP core is designed and implementated in this thesis which will be integrate into the MIPS MCU.This thesis analyzes and researches CAN Bus protocol and characters firstly,and then use "top-down" design method to full-custom design the controller based on GSMC 0.18μm CMOS process library and divided CAN Bus controller into some sub-modules based on the existing of CAN Bus controller system architecture,which including interface module,register module,timing module,data flow module and error management module.These modules are implementated and connected by Verilog HDL.The CAN Bus controller can construct and decomposition receiving/sending message,produce bit timing,detect error and so on.Then the design should be function simulation and analysis by Simvision of Cadence company.The result of simulation indicates that the design’s functions are correct Finally,CAN Bus controller program should be compiled and downloaded to the FPGA by Xilinx ISE.Then FPGA prototype verification is implemented by three CAN nodes whilch are consist of the CAN Bus controller,STM32 on-chip CAN Bus controller,CAN analyzer.The results show that this design can carry out CAN specification of Verision 2.0A’s functions,communicate speed up to 125kbps,achieve frequency range up to 3MHz and consume 62.7mW at the frequency of 3MHz,which meets the design requirements.The CAN Bus controller IP core which is designed in this thesis not only can be widely applied in the SOC and SOPC embedded system application,but also will prevent the program from running out in traditional independent CAN communication system with harsh EMI environment.
Keywords/Search Tags:CAN Bus controller, CAN2.0A, CAN nodes, Verilog HDL, FPGA
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