Research And Design Of CAN Controller

Controller Area Network is a kind of serial communication buses defined by ISO,which belongs to the category of fieldbus.CAN is obtaining more and more attention because of high performance,high reliability and being designed flexibly.CAN has been widely used in the automotive industry,aerospace industry,industrial control and other fields,and is developing towards more fields.The key part of the CAN network is CAN controller.CAN controller is a device which completes CAN communication protocol requirements and CAN controller is an important part which connects each control node to the bus. However,CAN controllers existing on the market are made according to standards, thus,CAN controller with different electrical parameters are different, which is not compatible.And a wide range of CAN controllers mostly are standardized product,so if people want to achieve additional functionality, it needs to take the additional circuit outside.Therefore, this paper presents an FPGA-based implementation scheme of CAN bus controller,gives the structure diagram,and detailedly describes the internal modules.In this paper, the CAN controller chip is designed by way of the top-down design, and is ensured the correctness of the design features through simulation tools. In this paper,the CAN protocol combining application is analyzed, the architecture of the entire CAN controller chip is divided.After an existing CAN controller (Philips company's controller SJA1000) being analyzed, the CAN bus controller is decomposed down into several functional modules.The acceptance filter module and the CRC module is completed mainly in this paper.And In this article,the principle of acceptance filtering and CRC check and the concrete implementation by the use of Verilog HDL are described, and the correctness of function modules are proved through the functional simulation on the FPGA development tool Quartusâ…¡,and their RTL-level circuits and the simulation waveform are gived.The shortcoming of the article is the lack of the detailed study and design of other modules such as the register module and bit timing logic modules. Further work needs to be done later.