The Design Of CAN Controller With Verilog HDL

As one of Field Buses, CAN Bus is widely used in many areas. And it is considered to be one of the most promising Buses. But chips available in the market are customized with all kinds of standards. So from the idea of developing ASIC, we can make use of FPGA to design an application specific CAN controller, hence to its functions, which is very meaningful.The main purpose is to complete the front-end design of CAN controller using FPGA. That means to complete the RTL-level design of Data Link Layer in CAN Protocol by using Verilog HDL, and to achieve its function, then to evaluate the design through the simulation on the platform Quartus II.In the thesis, our work is started from the lower level. Firstly, we analyze the CAN Protocol. Secondly, we split the entire CAN controller into several modules which are independent but associated with each other. Thirdly, their function and principle are introduced. At last, we manage to design the modules in RTL-level, to explain the idea and process, and to improve design for timing correctly by simulation. The simulation is divided into two parts: One is the logic function simulation, the other is simulation including information of the netlist and gate delay.Within the whole design, we split CAN controller into three modules. Register Logic Module is used to save the frame information, status and commands. We can transfer the data writing to and reading from itself. Acceptance Filter is used to check the identifier. Bit Stream Processor, the core part of the controller, is not only used to control bit stream between TXB, RXFIFO and CAN bus, but also complete the function of receiving and transmiting frames of data.In simulating, we suppose the clock cycle to be 10ns, and under this condition, the modules are found to meet the design requirements. In other words, we have laidthe foundation for incorporating more functions into CAN controller based on FPGA.