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Design USB2.0 Controller Based On Xilinx FPGA Technology

Posted on:2012-11-22Degree:MasterType:Thesis
Country:ChinaCandidate:Q GaoFull Text:PDF
GTID:2218330368977251Subject:Computer applications
Abstract/Summary:PDF Full Text Request
Currently, because of the USB2.0 interface have the advantages that low cost, high data transfer rate, easy to use, flexible, Hot Swap, etc, more and more researchers pay attention to USB2.0 Interface, and put into its study, which make the USB interface developed very fast, equipment type and the number increased dramatically. According to In-Stat report, the shipments of USB electronics add from 1.3 billion in 2005 to 2.79 billion in 2010. So, the research of this thesis has great value in use and broad prospects in application.In this thesis, a full-speed and high-speed USB2.0 controller has been designed based on the study on the principle of the USB protocol and EZ-USB FX2's CY7C68013 modular structure in Cypress Semiconductor, and through the FPGA verification and testing. Main tasks are as follows:First of all, the theory and the logical structure of the USB protocol have been studied in detail from several aspects, which mainly include the logic composition of the USB system, bus electrical characteristics, data transaction types, transaction and so on. Second, the FPGA design methods have been studied, the development of the designed chip and the software used in this thesis have been described. Then, based on the study on the modular structure of CY7C68013, the USB2.0 device controller has been elaborated from the transceiver UTMI module, memory and arbitration interface module, the protocol layer PL module, control and status register module, function module interface module and the translation of protocols modulel. Among them, in the package assembler PA module design we use the parallel algorithm to check the data packet by CRC, which reduce the hardware design and the delay issue in circuit, and reduce the cost of hardware. In the protocol layer module PL design, we deal with data packet using 3 buffers, which improved the separation rate of data and checksum, also increased the data transfer rate. Finally, based on Xilinx's ISE, each module has been described in Verilog HDL language, and we program the test for each module to exam its function which achieved good results and proved the feasibility of this design.In summary, the above results not only provide a USB feasibility reference for the manufacturers, but also enriched the theory in this respect and implementation techniques.
Keywords/Search Tags:USB2.0 Controller, FPGA, Verilog HDL
PDF Full Text Request
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