| The aim of this paper is to implement the decoder of turbo codes with FPGA. The iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper.Firstly, the paper introduces the theory of encoding and decoding of turbo codes, and the simulation analysis on the decoding performance of MAP,MAP_LOG,MAX_LOG_MAP algorithms with the C language in computer have been given. Secondly, according to a great deal of simulation results, the paper investigates the key design parameters which could greatly influence the performance of MAP algorithm.We choose the MAX_LOG_MAP decoding algorithm and use the technology of Altera and its Cyclone2 devices as the FPGA design scheme according to all the factors.Taking advantage of the technology of FPGA, The means, called"Top-Down"and"Down-Top", is applied in the design of FPGA in this paper. The whole system of decoding was partitioned into several functional modules which were implemented by VHDL. In the paper, the design of every functional module has been depicted in detail. A new method for interleaver in VHDL has been introduced which could save the interior resource of FPGA and improve the decoding speed. |
