The Optimization Design And Realization Of EEPROM Used For RFID Tag IC

RFID(Radio Frequency Identification)is a technology of contact-less automatic identification, and mainly used in transportation, storage, package, gate-prohibition, finance, books-management, files management and such like that. The RFID tag IC to be discussed in this paper is based on the standard of ISO 15693.It is divided into AFE, digital block and EEPROM according to function. EEPROM in this system stores all the information of the chip, each operation on the chip is the operation on the EEPROM. At the same time, the performance of EEPROM decides the performance of the whole chip because of its dominating power dissipated. A 2K Bit Ultra-low power embedded EEPROM IP has been designed and realized for passive RFID tag IC in this thesis, and taped out successfully.First of all, demonstrating RFID technology merit and its application are described, then tag IC design procedure and the whole RFID system work theorem are explained. Based on plentiful paper resources, this thesis describes the low-power solution and the realistic circuit for power strategy, address finding, high voltage generation and sense amplifier according to the analyses on the traditional solution of EEPROM with simulation waves after that. The whole design process is based on the SMIC 0.35μm 2P3M embedded EEPROM process and the Cadence and Synopsys EDA design environment, with which all the analog and digital simulation, layout and verification are done. The test shows that the chip achieves all the expectant performance.