Low-power Low-cost Passive Rfid Tag Chip Research And Design

RFID (Radio Frequency Identification) is a technology that incorporates the use of electromagnetic or electrostatic coupling in the radio frequency (RF) portion of the electromagnetic spectrum to uniquely identify an object. In recent years, it has been developing rapidly driven by various kinds of applications and has already been regarded as one of the most promising information technologies in the world.According to the application demands, lots of research has been done in order to design a low power and low cost tag chip.Firstly, the fundamental theory and link layers of UHF (Ultra High Frequency) RFID technology are discussed in this dissertation. The metrics of tag performance is illustrated and the corresponding optimization technologies are introduced.Secondly, for the low power design, sub-threshold technology is considered to be used in the digital circuit design of tag chip, and the key technologies and the related solutions are studied in detail. Then a sub-threshold standard cell library is built and used to implement the baseband module of tag chip based on the above analysis.Thirdly, for the low cost design, single-ended/differential-ended EEPROM cell is proposed and designed in standard CMOS process. Suppose that tag chip combines a 512k bits EEPROM module, the tag chip cost will be reduced to 81% compared with the tag chip integrated with conventional EEPROM cell. At the same time, a high performance ALL-PMOS charge pump is presented and implemented in standard CMOS process. Measurements results have shown that it can work in low power supply and higher power efficiency.Finally, a low power tag chip with two symmetrical RF channels and sub-threshold technology is designed and fabricated. The chip is based on EPC C1G2 protocol. Measurements have shown that the power can be reduced to 30%-50% in sub-threshold technology for the baseband module.