Design And Research On 12GS/s Ultra Wideband Data Acquisition System

With the rapid development of science and technology in the current era,the integrated circuit industry has made great progress.Among them,analog-to-digital converter ADC is an important field in the integrated circuit industry.With the improvement of communication bandwidth and speed,the requirements of acquisition system for data acquisition speed and bandwidth are gradually increasing.Multiple ADC time interleaving sampling technology has become the main scheme of designing high sampling rate and high-resolution acquisition system.However,due to the time mismatch error caused by time interleaving technology and the non synchronization between multiple ADC,the development of this technology is restricted.In order to realize the design of interleaving ADC board with high sampling speed and high precision,and eliminate the corresponding errors,a design method of high-speed and high-precision data acquisition system is proposed in this thesis.The specific research contents of this thesis are as follows:1.According to the concept and principle of ADC and time interleaving structure ADC,through the application analysis of time interleaving technology between high sampling rate and high-resolution ADC,this thesis expounds the design scheme of integrating four ADC chips on the board to realize interleaving sampling technology.The purpose of this scheme is to generate low jitter four phase clock generation module,micro variable delay limit module and data acquisition module to realize equal interval interleaving sampling of four ADC chips.2.The software logic program of the board is designed based on the board hardware.The main structure is the upper computer soft core AXI control mode.The upper computer communicates with the soft core based on Ethernet communication.After the soft core receives the data,the AXI bus transmits the data to the chip under each sub module,which can realize the direct regulation and test of the board in the upper computer.The design schemes of each driving sub module under the above architecture are introduced in detail,such as the driving scheme design of each chip in multi-level clock link,the design of data transceiver module based on JESD204 B module,and the design of storage module after data collection.3.In order to solve the mismatch error caused by time interleaving technology,this paper proposes a PC FPGA background inter chip calibration technology,which calibrates the gain error and time mismatch error between four ADC chips to an ideal range.Here,the calibration principle and calibration process of the above two schemes are introduced in detail.Under this scheme,the calibration of single tone signal input in the range of 10MHz-6GHz can be realized.The test results show that the performance of 12 Gsps 12bit adc interleaved board after final board calibration is ENOB = 7.31 bit,SFDR = 61.75 d B,SNR = 40.12 d B at a typical frequency of 500 MHz.The ENOB under the single tone signal of 10MHz-2GHz is not less than 7.2bit,and the SFDR is more than 58 db.After calibration at high frequency,ENOB shall not be lower than 6.9bit at 2GHz-6GHz and SFDR shall not be lower than 53 d B.The broadband signal test results show that the signal-to-noise ratio reaches 30 d B,which meets the design requirements.