Hardware Design Of Reducing Space Redundancy Module In Dual Modes Video Decoder Chip

With the application of multimedia video compression technique growing rapidly, demands for the quality of video become more higher. Video compression technique has became one of focal points in the high-tech field. H.264/AVC is the newest video coding standard of the Joint Video Team (JVT). Compared with the former standards, H.264/AVC has been made great improvement in computing accuracy and algorithm. AVS is the video coding standard that is developed by research center which is organized by Chinese Academy of Sciences. Comparing with the H.264/AVC, it has the same display effect and less decoding complexity and scale.Because the decoding complexity of H.264 and AVS is very high and it's hard to be emplemented by software in manner of real time, it's brought out the the decoder for H.264 and AVS by technique of SoC(System-on-a-Chip) in this paper. Based on analysis of some kind of intra-prediction algorithms, it's proposed a reconfigurable parallel intra-predictor IQ/IDCT decoder according to the similarity of the algorithms which makes the best use of resources and reduce the complexity of the chip and the cost.C model is designed to verify decoding algorithms and provide test vector. First, the chip is implemented by Verilog HDL. After FPGA verification is passed, the ASIC synthesis which bassed on SMIC 0.18μm technology library is done by Design Complier and the netlist of the chip is implemeted. The results of simulation and synthesis show that the decoder can achieve high-definition video coding in real time.