Font Size: a A A

The Two Dimensional IDCT Algorithm Based On The Distributed Arithmetic Fast Direct Method And Its IP Core Implementation

Posted on:2005-09-08Degree:MasterType:Thesis
Country:ChinaCandidate:X K LuoFull Text:PDF
GTID:2168360152465845Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Since orthogonal DCT/IDCT has the next best performance for highly correlated signals, appropriate computational complexity, reparability and fast algorithm, it is widely used in digital signal processing, especially for image and video data compression/decompression. And these processes recently apply to battery-operated system like wireless communication equipments with development of media and digital communication technology. It becomes imperative to develop DCT/IDCT algorithm and its VLSI implementation, especially to develop low power and high performance algorithm and its VLSI implementation as one component of these energy-crucial desktops. Thus it is significant to design an application specific EDCT IP core and it is important component of MPEG decode SoC chip.This paper presents the two Dimensional IDCT algorithm based on the distributed arithmetic fast direct method and its IP core implementation. The low power algorithm level design reduces gates count and irregularity architecture of the algorithm implementation. The design code has been optimized carefully in RTL level. The core uses combinational logic optimized to generate the sum of accumulation instead of the conventional ROM-based Look-up table distributed arithmetic. The core has been simulated rigorously in gate level, and the result validate it is low power, low gates count, high precision and high throughput. It is compliant to IEEE 1180-1990 number precision standard, supply JPEG image standard, MPEG (MPEG1, MPEG2 and MPEG4) digital video standards H.261 and H.263 video conferencing standards. It can be widely use.Finally, this paper dose deep reaches on simplify logic network, and present a new method used to simplify complex combinational logic and reduce logic redundancy. A circuit used to compute 4-variable inner product is designed with the method. Characteristics of the circuit are high performance as low gates count.
Keywords/Search Tags:IDCT, direct 2-D method, DA, IP, ASIC, FPGA
PDF Full Text Request
Related items