The Realization Of LDPC Encoding Based On FPGA

LDPC(Low Density Parity Check) code is a key technology of the future broadband wireless commu- nication to raise the communication quality and the data rate.The thesis mainly studies the implementation of the LDPC code in the practical communication system.The practical communication system requires that the LDPC code with the MSK modulation owns the system error bit rate Pe＜=10^-4 in the condition of signal noise rate SNR=2dB.Based on the implementation background,the thesis takes up with design and realization of LDPC encoding based on FPGA.The encoding complex of LDPC code is linearly proportional to the square of code length.Large complexity of encoding becomes an obstacle of hardware realization.In the light of the expect target of the practical communication system, by the simulation analysis on the constructed algorithms of parity-check matrix and the factors that affected the performance of LDPC code,the thesis introduces three kinds of design schemes of encoding including direct lower triangle encoder, serial QC-LDPC encoder and two-stage QC-LDPC encoder.And the encoders adopt 1/2 code rate and two kinds of code length 1024 and 2048.For every kind of encoder,the thesis designs its integer structure and deeply studies its function models.After design the timing simulations of encoders are implemented with MODELSIM software.Then based on timing simulations results and sythesizing reports,three kinds of encoders are compared and serial QC-LDPC encoder is thought to be encoding method of hardware realizing at last.Finally,the serial QC-LDPC encoder is realized by FPGA and is test.The correctness and hardware realization are validated by MATLAB emulator and serial interface communation tools.