Design And Implementation Of Configurable LDPC Encoder Based On FPGA

LDPC code (Low-Density Parity-Check Code) is one of the high efficient forwarderr-correcting codes. Because of the characteristics of good error correction performanceand relatively low decoding complexity, LDPC code has attracted a lot of attention andbecome a field of channel coding. In order to adapt to different channeltransmission environment, the encoder needs to be able to adjust the encoding schemeaccording to the feedback information of the receiver to improve the effectiveness andreliability of the communication systems.In order to implement the configurable LDPC encoder based on FPGA, the structure ofbinary LDPC codes is studied, including MacKay’s construction method, PEG constructionmethod and PS construction method. And a comparison has been done based on MonteCarlo simulation. Based on the comparison result, PS construction method is chosen toconstruct6LDPC matrixes. Gaussian elimination coding, coding based approximationalgorithms and quasi-triangular recycling code encoding are studied. Coding complexity ofdifferent algorithm and the corresponding required storage space are analyzed. Basing onthe results, quasi-cyclic codes are chosen to implement the LDPC encoder basing on FPGA.A serial quasi-cyclic LDPC encoder and a parallel quasi-cyclic encoder with the codelength of3920are designed. And the structures of the two encoders are given. The basicfunction partitions of the two LDPC encoders are described by Verilog HDL. And the twoencoders have been implemented on FPGA. According to the comparison result of the twoencoders’ encoding rate and occupation of the resources, the serial quasi-cyclic encoder hasbeen selected to implement configurable quasi-cyclic LDPC code encoder with6codelengths. A GF(8) LDPC encoder with length of90and rate of2/3is implemented by VerilogHDL. And the timing simulation of the encoder is given.An automatic test program for the configurable LDPC encoder and GF(8) encoder isachieved by Visual C Plus Plus. It sends message sequence to the FPGA development boardthrough computer’s serial port. And the FPGA development board sends back the encodedmessage sequence. Then the program compares the encoded sequences which are encodedby FPGA and the test program. It is proved that the LDPC encoder works well. A testsoftware is designed by Visual C Plus Plus. The software generates message sequence and a white Gaussian channel. The software connects with the encoder and decoder through theserial port. The test results show that the performance of the LDPC codes is similar withtheoretical value.