The Research And Implementation Of Low-Power Deterministic BIST

In order to solve high power consumption of BIST in deep submicron process, a new single/double input change deterministic test pattern generator is presented based on a single input change technology and 2-bit twisted ring counter, and it can achieve low power test.The proposed low-power deterministic BIST test pattern generator has low test power, small area overhead, short test time and can reach the higher fault coverage. First, in order to achieve maximum fault coverage, it uses the deterministic test scheme. Unlike traditional deterministic test schemes storing the deterministic seeds, the presented scheme saves the control signal bits in ROM. With these bits, the deterministic seeds and patterns can be generated by single/double input change. It is beneficial for area overhead because the length of control signal bits are just about 1/2 of deterministic seed's. Secondly, the SDIC units are used to generate the deterministic seeds and patterns, which ensure that only 1 to 2 transitions are generated between the adjoining two test vectors and the test power consumption can be greatly decreased. Finally, the proposed scheme uses a 2-bit down counter to limit the number of deterministic test vectors during the seed reseeding, and the test time, total energy consumption and redundancy test vector are all reduced.In addition to optimizing the hardware architecture, the corresponding seed selection algorithm and three different x specified algorithm are also presented. The design principle of algorithms is that selecting the candidate seed set which have minimum area overhead in seed selection algorithm process, and then deciding the final deterministic seed using x specified algorithm. Because each x specified algorithm has different design and purpose, it should be selected according to the actual situation. Algorithm 1 is based on the principle of longitudinal compression, and it makes that each seed can compress test vectors as much as possible to reduce the area overhead. In order to shorten the test time, algorithm 2 selects the final deterministic seed whose hamming distance is the shortest from the set of candidate seed, and the test cycles for new deterministic seed can be decreased. Algorithm 3 uses variable-length coding, namely lateral compression, to achieve the same purpose for reducing the area overhead.In order to verify whether the presented scheme can meet the expected requirement, the paper uses ISCAS'85 standard circuit as CUT (Circuit Under Test, CUT), uses the Altanta tool to generate ATPG deterministic test vector set, uses Matlab tool to achieve seed selection algorithm and three different x specified algorithms, and gets the three different set of control signals and performance results. Experimental results show that the average power reductions are up to 42.36%,32.32%,38.94%, and the test length reductions are up to 77.6%,86.1%, 84.3%, and then the test data storages are decreased by 79.4%,65.2%,68.1%, respectively. What's more, this paper implements hardware structure based on Verilog and the simulation results are in line with expectations.