Design And Optimization Of PCI Bus HDLC Processor

With the fast development of telecommunication networks, a dominant PCI bus in a computer will play an important role in optic-fiber communication access and multimedia integrated broadband services with high data transports. Therefore, it will have a bright future to develop VLSI chip based on a PCI bus and related a communication protocol.The research of this dissertation is an important part of the project"PCI bus HDLC frame engine and data link manger"founded by the Office of Science and Technology of Jiangsu Province. The key intention is to present the design of a multi-channel high speed HDLC data processor that can process 128 logic channel HDLC data simultaneously. This Multi-channel HDLC processor connects with 4 channelised E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 31. Compared with other commercial chips of the similar type, this circuit structure takes more advantages in chip resource's utilization and channel management.Based on thorough analysis of HDLC IP core, the HDLC IP soft core's top function definition and structure partition, detailed description of all level modules were finished in the dissertation according to the Top-Down high-level design process of digital ASIC system. Every level module of the data path and controller of HDLC IP core was designed and every unit's design of HDLC IP core was programmed with the Hardware Description Language (Verilog HDL). All modules of the IP core was programmed, debugged, placed and routed in the EDA environment of ISE and the logical synthesis was done with the Synplify software. The function simulation and the gate-level simulation were done in the ModleSim EDA environment.At the same time, the description style and the design skills of Verilog HDL were discussed in the dissertation. The HDLC IP soft core existed in two ways, namely, source code in the synthesizable Verilog HDL language and the standard NETLIST document of EDIF. Meanwhile, the thesis did some useful research in the methodology through practising the whole Top-Down high-level design process of IP core.