Research On The Embedded Flash Memory Intellectual Property Testing For Electronic Payment Chip

To faster time to market and lower development costs, Embedded Flash Memory Intellectual Property(EFlash IP) is used increasingly in System On Chip(SOC). As the EFlash memory capacity increased and the semiconductor size decreased, the EFlash memory physical faults become more than acceptable. In order to ensure the quality and stability of the chip, reduce the cost of chip packaging, maintenance, effectively for the chip must be test.The problem is how to eliminate these faults quickly and efficiently in an economic way. In order to solve the problem, this paper studies the design and implementation of EFlash IP test circuit.Firstly, the paper studies the EFlash fault models and the classical test algorithm, and use the EFlash serial interface test plan to solve the faults. The Built-In-Self-Test(BIST) circuit include the serial to parallel and parallel to serial converse circuit,and the timing circuit of EFlash read, program and erase operation,and the improved checkerboard algorithm which the background data can be configuration and the test steps can be combined. This plan can enhance the testing efficiency and the flexibility of EFlash observations. In order to verify the function and timing of the test circuit, we use Verilog and Vera language to build a simulation platform, and give some analysis results.Secondly, this paper introduces the design of EFlash tester based on MIPS development board after the chip is taped out successfully. It describes the detail of ATE-DUT system architecture, and the hardware and software integrated development environment. It also focuses on the implementation of firmware test and tester work flow.Finally, this paper introduces the automatic test equipment and test plan of wafer. Based on the analysis of the engineering data of the wafer test, the enhanced product yield rate of EFlash redundancy repairment design in the wafer is summarized.This paper can provide reference for EFlash IP test circuit design.