Design And Verification Of PWM IP Core Based On SoC

In industrial control,Pulse Width Modulation(PWM)as an effective digital signal control analog circuit technology is widely used in power electronics,motor control,mechanical control and other fields.In order to meet the demands of industrial control,it is necessary to integrate the PWM generator in the SoC chip.Based on the SoC technology,this subject has completed the design and verification of the four-phase PWM IP core that meets the APB bus interface standard.The main work of the thesis is as follows:In connection with the PWM function requirements of industrial control chips,the front-end design of the PWM core has been completed,including overall architecture definition,module function division,module principle design,etc.After the design is completed,the PWM core has rich functions such as input capture,output comparison,and dead time insertion.On the basis of researching PWM applications at home and abroad,the PWM function has been optimized,such as the use of a clock selection circuit to solve the glitch phenomenon that occurs during clock switching;buffer registers are set to ensure a smooth transition of the output waveform boundary during register configuration;increase The output waveform category expands the application scenarios of the PWM core.These designs improve the functional reliability of the PWM core.In addition,the PWM core bus interface conforms to the APB bus protocol,and the CPU can communicate with it through the bus,which reflects the functional flexibility of the PWM core.Based on the SMIC 0.18?m process and ASIC design flow,the logic synthesis and layout of the PWM core have been completed.The conversion of the RTL code to the gate-level netlist is completed by the synthesis tool DC.The integrated PWM core area is about 52000?m~2 and the number of gates is about 9.4 k.When the integrated target frequency is 50MHz,the obtained slack=8.69 ns,which meets the timing requirements of the setup time.The conversion of the PWM core gate-level netlist to the digital layout has been completed through the placement and routing tool ICC.The layout has passed the DRC and LVS checks of the ICC.The clock skew is 0.0934 ns,which meets the timing requirements,and the power consumption is 2.4490 m W.Based on simulation and verification tools,functional verification and formal verification of PWM core are completed.According to the module function points of PWM core,the verification plan of each module is formulated to complete the module level verification,and the SoC minimum system is built to complete the system level verification.The correctness of the PWM core function is demonstrated by analyzing the verification results.In addition,the formal verification of PWM core is completed by comparing the matching points between the RTL code and the gate netlist.In this process,a total of 868 matching points are verified and passed,which proves that the gate netlist of PWM core is consistent with the function of RTL code.Based on the above-mentioned research and work,this subject has completed the front-end design,functional verification and back-end implementation of the PWM core,which can provide industrial control SoC chip designers with a PWM IP core that can accelerate the design progress,has multiple functions,and is flexible and configurable.