An intellectual property core to support communicating sequential processes

This thesis describes the major architecture features of an instruction set processor architecture that has been specifically developed to support the Communicating Sequential Processes (CSP) paradigm. The processor architecture is fully described as an Intellectual Property (IP) soft core written in the VHDL hardware description language where it can be used to create a single chip parallel processing environment, using commercially off the shelf, Field Programmable Gate Array (FPGA) technology. Unlike other such IP cores that are present in the market place, this CSP-style core processor incorporates instruction set support for low latency high bandwidth synchronous message passing between similar core processors that reside within the same integrated circuit medium. The simplicity of the instruction set allows for fine-grain implementations that can employ a large number of such CSP processors that can be interconnected together using a topology whose structure is determined by the needs of the application.