Design Method For High Definition Multimedia Interface Transmiter

We focus on the design and implementation of HDMI_Tx chip architecture, especially its audio, video, bus, packet generator, and hdcp module in detail in the thesis. To overcome the difficulties of the design, We provide analysis method, and verify the function of the design by simulation in RTL level and by FPGA implementation. The feasibility of the design is thus assured. In the design process, according to compatibility test of HDMI & HDCP, designer must make design in robust, minding the error bit rate in data transmitting in communication channels, aslo taking self-recovering from abnormity into account. In the video interface module, as to the down stream HDCP module's demand, it has to recover the syncs in video stream, and sets down method to be cautious to set and update the video format.During the verifcation process, a random test pattern generator is designed in order to obtain higher coverage probobility. The video frame described in CEA861B is shortened and . the time for test is reduced.To depress the cost of the chip, we need not only an efficient algorithm but also a minimum power consumption and a minimum chip area, so that the product may survive in consumer electronic market competition.The RTL part of this project is designed on the platform of QuastaSim6.3 of Mentor Corp. in verilog IEEE 2001 language. SystemVerilog IEEE1800 language is used for verification process. In the next verification step, Synopsys Corp VCS0606SP1 helps a lot by DesignWare IP and VMM library.The Virtex-2 Pro of Xilnix Corp. is used for FPGA verifcation.