Research On The Design For Testability Of The Digital Core Of The Interphone Transceiver And The Verification Of Its Interface Circuit

In the modern IC design, the scale and complexity of the chips increase exponentially. To assure the functional integrity of designs becomes more difficult and costs more time and resources. Today functional verification has become a bottleneck of large scale chips design. It increases the difficulty of chip test. On the other side, the mis-doping and impurity in the IC process cause the defects, resulting in the abnormal operation of the chip. There comes several new verification techniques in recent years, for example, assertion based verification, constraint random stimulus and etc, while in the manufacture test field, the introduction of Design-for-testability has simplified the debugging due to the self-defect in the chip enormously.By the sufficient investigation, the dissertation has studied and accomplished something as follows:Assertion based and constraint random stimulus verification is a new kind of verification methodology, which can greatly improve the efficiency according to its developing rule. The dissertation utilizes the SystemVerilog based platform and concentrates on the digital core of SRT3700, a walkie-talkie chip; the verification environment is ModelSim6.2g, Debussy and Perl. The Sub-block of digital core is co-simulated with Matlab and ModelSim. Thus the function of the core is fully verified to be correct.In the DFT field, the digital core is designed with full scan methodology including adding the DFT wrapper, modifying the clock generation block, etc. Though scan synthesis with Cadence RTL Compiler and ATPG with Mentor Fastscan, the core reaches the satisfactory fault coverage and accomplishes the design flow through pattern simulation.At last, the design is implemented by SMIC 0.18um process and is tested successfully.