Verification Of Chip Clock Module Based On SystemVerilog

Integrated circuit design is a complex task that is extremely afraid of errors.With the continuous increase of integration scale and the continuous evolution of process nodes,any error may cause great losses,making verification work more and more important.At the same time,the amount of verification work is increasing day by day.In the development of digital chips,verification work can account for up to two-thirds of the entire project.Even with such a large effort,the problem of tapeout failure due to verification loopholes or errors is still As it happens,how to ensure the comprehensiveness of verification has become a key point in current chip.design.The clock module can be compared to the heart of a chip.The start-up and normal operation of the clock are the basic guarantees for the realization of chip functions.Therefore,a comprehensive verification of the clock module is extremely important in the chip verification work.In this paper,the clock module verification of the chip adopts a hierarchical verification environment based on SystemVerilog,expounds the necessity and specific methods of verification process,and analyzes the verification methods of formal verification and simulation verification and their respective advantages and disadvantages.At the same time,an assertion-added verification method is adopted,and assertion verification is added in the verification environment based on the characteristics of the clock module,which increases the completeness of the verification.Since there are no complex transmission protocols and logic functions in the clock module,the verification components are reorganized and simplified when the verification platform of the clock module is built,and the functions of the reference module and the comparator module are completed through the monitor module,which effectively improves the reliability of the verification platform.Reusability and efficiency of verification work.The number of directional test cases is proportional to the number of decomposed function points,and the number of random test cases is proportional to the complexity of the protocol.For the development of test cases for the clock module,since there are no complex logic functions and transmission protocols in the clock module,most of the test cases are directed tests.At the same time,because the clock module has a lot of function points,there are as many as 277 directional test cases,so in this project,a script is used to generate a part of the test cases.This method greatly reduces the time cost of work,and at the same time reduces Human error written by hand.Through regression testing to ensure the correctness of all test cases,through the analysis of coverage results to ensure the completeness of the clock module verification work.According to the analysis of the chip clock module in the actual project,the key functions of the chip clock module mainly verified,including the check of the read and write functions of the register,the input excitation vector is used to input the excitation vector and the data is read out to compare and check its reading and writing.Performance;check the correctness of the connection between the register and the interface,write to the register by bit-wise flipping to observe whether the interface signal is correspondingly flipped to verify the correctness of the connection;check the clock frequency reduction function and switch function on the two data buses,Check the frequency of the clock in different working modes;check the performance of the phase-locked loop,first check the correctness of its function by configuring its register control bit,and secondly,by configuring different working modes for its output clock frequency and internal parameters Check;check the control logic of the physical layer interface of the transmission clock,and check its switch and selection functions by configuring the register.Finally,the progress of the verification work is estimated by the pass rate of the test cases in the regression test,and the final requirement is to achieve a 100%pass rate,that is,to ensure that all test cases are correct.Check the adequacy of the verification work by collecting and analyzing code coverage and functional coverage,and supplement the integrity of verification by adding targeted test cases.Based on code coverage,functional coverage,and assertion coverage,the test case pass rate in regression testing is the main body.In strict accordance with the process-based verification method,the assertion verification is added to check the signal timing to ensure the correctness of the verification.And completeness.In the actual project,the written Perl script automatically generates test cases to significantly improve the efficiency of the verification work.The checked register signals are as many as 200.The actual work of the project proves that the script is true and effective,which can greatly reduce the verification work time of write test cases.