Function Verification Of Subsystem Of Video Signal Process Chip

Function verification becomes the largest bottleneck of design flow. Statistics show that it takes 60% to 80% efforts, but 2/3 or more chips must be taped out again to modify functional bugs. Simulation-based verification is the primary method of function verification, while the traditional method suffers from some deficiencies (lower observability, controllability and automation). How to implement function verification quickly and efficiently is one key question in IC verification field.Based on the Research of Video Signal Process Chip (VSPC) from Tianjin Municipal Science and Technology Development Project, this paper describes the function verification of VSPC Subsystem (VSPS). A new strategy for the verification of VSPS is proposed including verification route, verification method, verification flow, verification language&tool. The paper analyses VSPC, and then separates it into OSD and format conversion subsystem. According to the feature of two subsystems, the paper establishes a route combined layered verification with bottom-up verification and appropriate verification method. Referring to the current popular verification technology, the paper describes some key points of verification flow including stimulus generation combined direct test with constraint random test, result checking combined assertion with data comparison, coverage metrics combined function coverage with code coverage and layered testbench establishment based on VMM methodology. The paper chooses SystemVerilog as verification language and Questasim 6.2e from Mentor Graphics as simulation tool. Finally, according to design specification of two subsystems and strategy above, the way of stimulus generation, result checking and the architecture of testbench are expatiated, and function verification of two subsystems is carried out.Simulation result shows that the verification strategy can make a good join of stimulus generation, result checking and coverage metrics, improve the observability, controllability and automation of simulation process, reduce the develop cycle, and guarantee the successful tape-out.