Research And Design Of VMM-based Testbench For Image Processing Subsystem

Functional verification has become the bottleneck of projects that developing Very Large Scale ASIC and System-On-Chip. Directed test, which is the traditional verification method, can not meet the requirement that verifying a complex design fully. For the purpose of obtaining higher verification productivity, a series of advanced methods and languages have been developed. Based on the above progress, the verification methodology offers a complete solution for Module-Level and System-Level verification, which improves the verification efficiency by making testbench more automatic and reusable.The functional verification for Image Processing Subsystem is studied in this thesis. This system, which is the core algorithm unit of a Multi-standard Video Post Processing Chip, is used to implement the conversion among multiple VESA video formats with the same frame frequency. In this thesis, the Verification Methodology Manual (VMM) is adopted as the main principle for developing verification plan that describes the function points to be covered. The testbench is built according to the layered structure which is recommended by VMM, and all the components are self-designed. The testbench can generate 36 kinds of VESA video formats, and supports the checking of the correctness of DUT's output timing and the evaluating of the image processing quality of DUT. Several advanced technologies are integrated into the testbench, such as constrained random test, coverage-driven verification, transaction-level verification and assertion, while Blueprint and Callback are also used for supporting the executing of more test cases, which enhances the stability of the verification environment and improves the reusability. A dynamic constraint modifying technology is also studied, which enables users to control the coverage's increase.Simulation result shows that this testbench can support multiple test cases including directed test and random test according to user's configuration, and its high-level automation is also proved, which will improve the verification efficiency effectively.