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Optimization Of H.264 Decoder Based On TMS320 DM642

Posted on:2008-02-27Degree:MasterType:Thesis
Country:ChinaCandidate:S J ZhangFull Text:PDF
GTID:2178360245992077Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
H.264/AVC is the newest video coding standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The main goals of the H.264/AVC standardization effort have been enhanced compression performance and provision of a "network-friendly" video representation addressing "conversational" (video telephony) and "non-conversational" (storage, broadcast, or streaming) applications.The TMS320 DM642 device is a fixed-point digital signal processor (DSPs)has eight highly independent functional units and 64 32-bit general-purpose registers.At a clock rate of 600MHZ, the DM642 device can perform up to 4800 million instructions per second (MIPS).The powerful capability of data processing and interface make DM642 very fit for the video and imaging applications, for example, the audio/video transmission and security monitor over IP (Internet Protocol) and wireless networks.The main task of this paper is to introduce how to develop and optimize the H.264"baseline"decoder on the hardware platform based on TMS320DM642. The source program adopted is the decoder part of the"JM"which is one of the open H.264 codec software. The effective method to improve the implementation efficiency of the video coding algorithm on DSPs is to"tap"the parallelism and memory resource of the processor for the requirement of real-time system. Three aspects of job have been done on the JM source program: the first is to reduce, modify the source program and port it from personal computer (PC) to the DSP platform; the second is to optimize the data transmission and memory space using the Enhanced Direct Memory Access (EDMA) controller of DM642; the third is to improve the kernel algorithm and code of the encoder using intrinsics and linear assembly language, which can improve the parallelism inherent in the H.264 encoder. In the end, an embedded real-time H.264 decoder with lower-complexity and higher coding performance was provided.Our H.264 decoder can decode 30~40 frames per second (fps) for QCIF resolution video. The decoded video pictures provide high subjective and objective quality.
Keywords/Search Tags:CODEC, TMS320DM642, JM, H.264/AVC
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