Implementation And Optimization Of H.264 CODEC Software Based On TMS320DM642

The H.264 AVC video compression standard has achieved a significant improvement over all previous video compression standards. But the H.264 standard is significantly more complex than any of the previous standards. Consequently, the H.264 standard is expected to be significantly more demanding in terms of computations and memory requirements. Since any decoder should be able to handle all"legal"bit streams, making the decoder implementation even more complicated. More over, the development of an embedded CODEC implementation where the internal memory size is limited is a challenging task.The TMS320DM642 Digital Media Processor (DM642) is the highest-performance fixed-point DSP from Texas Instruments. The DSP core processor has 64 general purpose 32-bit registers and eight highly independent functional units-two multipliers and six arithmetic logic units with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.My main task is port and optimize H.264"baseline"CODEC software on the Texas Instruments'TMS320DM642 Digital Media Processor. Discussed in detail the procedures to the hardware platform of the port process. Optimization process have two process, firstly optimize the intra-frame and p frame by using the ahead break skill, secondly according to the hardware platform optimize the software by intrinsics function.After the optimized, the encoder can provide 2-3 fps encoding performance for CIF resolution video now. The decoder can provide 20-30 fps decoding performance for CIF resolution video now.