The Design And Implement Of EDAC Circuit For Memory On FPGA

By the radiation in space environment, the SRAM on satellite may experience SEU(Signal Event Upset). SEU will cause a certain data in memory changes from one steady state to another steady state, and this changing in memory may seriously lead to the collapse of the on-board computer system. As a result, it is necessary to find a way to correcting or tolerating the errors. There are many ways to achieve fault-tolerant or error-correcting. The topic using the method of error-control codes to achieve SRAM Error correction. This paper details the design process of the circuit structure, simulation and debugging of FPGA process. It has very important significance to the on-board computer'reliability and minimize the soft errors of memory caused by SEU.Above all, error-correction codes theory is mentioned in this paper. Considering the SEU occurred at a scale of small probability, we demonstrate the advantage and feasibility of various error-correction codes on the application of memory, and the ultimate choice is (13,8) Hamming codes. Then an EDAC (Error Detection And Correction) circuit with a simple control method and shorter critical path is described in this paper. Apart from the normal correction function, the circuit designed by Verilog can write the corrected data back to SRAM. Finally, a debugging method using FPGA is mentioned in this paper.In this paper, the EDAC circuit is tested on FPGA. At first, the CoreMP7 Development Board was briefed. Then according to board of existing resources, with repeated testing and revising, a testing platform was finally made. The platform can be used to test the design of this paper EDAC circuit function.