Study On Key Techniques Of Spaceborne DSSS Receiver For Satellite Based Navigation System

Spaceborne navigation receiver is the important part of the Global Navigation Satellite System(GNSS), which can be used to receive the uplink signal and inter-satellites link. It’s more difficult to study the receiver’s technology of the sapceborne than the technology of the ground because of the restriction of the limited of the hardware resource and space environment. The conflict among hardware resource, high performance, reliability and realtime are prominent particularly. The front-end optimal design, finite word-length effect, high precision carrier tracking,and space memory anti-radioactive are researched around in this dissertation.And the primary researches and contribution in this dissertation are summarized as follows:(1) Aim at the problem of non-distortion sampling and optimal quantization of the analog-to-digital converter to the direct-sequence spread signal, a model with filtering, sampling and quantization integrative effects is established. Based on analyze the quantization distortion and sampling rate offset and dithering effect to the output performance, a new analytical method of output signal to noise ratio is educed.Open out the output performance effected by the presampling filtering, sampling, and quantization. The conclusion can be the theoretics to optimize designed of the receiver’s front-end.(2) Aim at the problem of the word length effect to the performance of the digital signal processing, a universal model of the non-linear signal processing of the receiver is established.The influence on output SNR of finite word length effects of the input signal of PN code acquising, carrier and phase tracking are analyzed. An improvement of ant colony algorithm to optimal word-length is proposed. Base on satisfy the performance demand, a method of design the word-length of the module constitute the system which minimize the cost is proposed. The researchs can be apply to the the word-length optimal designed of the reciever.(3) Base on the contradiction to the high resource limited and high performance of design to the carrier phase lock loop, a improvement discriminator based on phase pre-compressed multiplication and a menthod based on Coordinate Rotation Digital Computer(CORDIC) on actangent discriminator implement are proposed separately. The new discriminator’s max convergence region is π, the traditional multiplication discriminator’s convergence region isπ/2 however.The new discriminator has wider linear range and high lock loop precision. The new menthod’s convergence time is 3 times than traditional method at the same error(≤2-8). The precision is 30 times than tradictional menthod at the same iterative times(8 times).(4) The formulations of mean time to failure and reliability are deduced under the soft errors of space memory systems affected by SEU(single event upsets). An approximation and quickly analysis in the calculation of mean time to failure for memory systems is produced. The optimal cost function which satisfied the system reliability is obtained by the analyzed of the effect of the mean time to failure from four aspect : codeword length, scrubbing interval, error correction capability and memory size. The results show that the system reliability will be improved by reduced the scrubbing interval and increased the error correction capability of the ECC(error correct codes). All above of the elements of the cost function will be considered to reach the system reliability. The research can be the academic direction of the optimal design of the space memory against error.(5) Aim at the muli-bits errors of memories caused by SEU read-writed with the whole byte, a(26, 16) interlaced code was proposed for less than two random errors correction, less than quadruple adjacent error correction(DEC-QAEC), which was composed by two systematic(13, 8) codes for correcting single errors and adjacent two errors. It can correcte more error than the tradictional(13,8) circle code at the same memory overhead and real-time performance. Aim at the muli-bits errors of memories caused by SEU read-writed with the whole block, a)1,,(21nnA code with 1n lines and 2n rows is improved.It has less than 1 decoder and can be correct more than 11n? burst errors than the same interlaced code of 1n times interlaced. It has applied to the occasion of high limited to hardware resource and real-time performance.Finally, a scheme based on space telecommunications radio system is proposed. The spaceborne uplink DSSS reciever of xx navigation system is implemented. Test onground and On-orbit experiment results show that reciever’s performances of power, reliability and range measurement are reach or beyond the design performance.The research results have also been used in GNSS equipment successfully such as precise range code module and basical user receiver.