Research On ΔΣ Modulator And Behavioral Modeling Of Fractional-N Frequency Synthesizer

With the development of communication technology, the frequency synthesizer with high performance has becoming hotspot. The PLL fractional-N frequency synthesizer is for this demand. Although it overcomes the shortcomings, such as small loop bandwidths and big phase noise in the integer-N frequency synthesizer, it has its own disadvantage that is fractional spur. Several technologies come out to eliminate the fractional spur.ΔΣModulation is the one that is the most successful.This paper includes two aspects of contents:First, this paper is focused on the research of theΔΣModulator used in PLL fractional-N frequency synthesizers. A comparative study of two typical Modulators (MASH and Single-Loop Multi-Bit) is conducted to provide detailed design considerations and guidelines for this block. And at last this paper achieves a MASH4 for the item.Second, to speed up the simulation of PLL fractional-N frequency synthesizer, this paper designs a time-domain transient model and frequency-domain phase noise model with Matlab and Simulink. The transient simulation and phase noise analysis can be done quickly with these two models. The transient simulation takes about 45 seconds for a 400MHz output. And phase noise analysis can be done within 1 or 2 seconds. Via this, the system design for deciding or changing blocks'parameters is well constructed.