Design Of Charge Pump And Loop Filter For Frequency Synthesizer

The wireless communication technology and market have been growing rapidly recently. The hign demand market is a driving need for higher integration in the wireless transceivers. With the development of integrated circuits technology, it is becoming feasible to integrate the RF front-end together with the baseband in the low-cost CMOS technology. The frequency synthesizer is a key building block in the RF front-end of the transceivers. It is used as a local oscillator for frequency synthesizer translation and channel selection. This thesis start with the principle of fractional-N PLL frequency synthesizer, then discusses its advantages and disadvantages comparing with other strctures. The most important modules-charge pump and loop filter are introduced and designed in detail.Aimed to the problems in popular charge pump designs, we put forward a new charge pump structure, adopt differtial inputs, single output, add a dummy branch, decrease the spur of charge pump(spur<70dBc), and make it work in a very high frequency (>100MHz). We alse analyze the function and the popular structure of loop filter in frequency synthesizer, discuss the disadvantage of common loop filter (large area), put forward a new loop filter-dual path loop filter. The new structure adopts two charge pump as its inputs, minishes the capacitance(<1.4nF) through adding the two signals. At last, the design, simulation, optimize and verification of charge pump and loop filter for fractional-N frequency synthesizer have been accomplished, based on UMC 0.13μm RF CMOS process.