Research On DFT Methodology Based On STN LCD Driver And Controller

As the complexity of Integrated Circuit design and process is improving, the cost of test and its ratio in the total NRE of IC design are both rising greatly and the IC's test is becoming more and more difficult. The conventional Automatic Test Equipment (ATE) can not satisfy the requirement of Integrated Circuit's test. Design for testability (DFT) technology has become the main method to resolve the issue of chip test. Design for testability techniques offer one approach toward enhance testability by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is rising as the cost of testing decreases, there is now a growing interest in these techniques for VLSI circuits. Our project is a 4-gray scale STN LCD driver and controller. We compare the mainstream DFT technology in performance aspect and bring forward our structured DFT strategy. Full-scan testing for core logic and MBIST for embedded memory are adopted for the chip testing. The ameliorated March test algorithm which is sourced from bit-oriented March test algorithm insure 100% fault coverage for stuck -at fault,stuck -open fault,transition fault,address decoder fault. Through adding a very small number of circuits the testability problem was removed. Three scan chains of multiplexed flip-flop style be constructed to achieve a SAF(stuck-at fault) in the chip, and the test pattern was generated in TetraMAX. High test coverage is achieved through ATPG faults simulation. The cost of DFT is adding 4 percent area and 11 pins. In a conclusion the structured DFT of the chip shows a good result to meet production manufacturing requirements.