DFT Implementation And Physical Design Based On 28nmDDR PHY

In recent years,in order to shorten the time-to-market of chips,improve efficiency,and save costs,SoC(System on Chip)has begun to promote the use of IP(Intellectual Property)cores that can be reused.The mainstream speed of DDR4 has reached 2133 Mbps,which is more widely used in the industry.high.The DDR PHY(Physical)that matches DDR is often used as a high-speed IP core.When DDR PHY is used as IP,because users do not fully understand the internal architecture and design,users often use DDR PHY When a black box is used for processing,the input and output ports are integrated into the SoC during normal use,so the port lacks the controllability and observability that it should have,which brings huge benefits to the integration and verification of testability design.Difficulty.This article is to conduct its own DFT(Design For Testability)integrated design and verification on the high-speed interface DDR PHY of the off-chip memory in a wireless connection chip,and present the DFT structure of the test DDR PHY,as well as the verification method and results.The innovation and difficulty are embodied in the following aspects:(1)Test the digital logic of DDR PHY and the internal registers of the PHY and each node of the entire circuit.By planning the test circuit for the original logic,including the test clock and test mode division,the DFT circuit is inserted into the scan test,and the shift register is used to input the test data,and then capture and observe whether the output value is correct.The test method includes the Stuck-at test(the internal flip-flop is replaced with a scannable flip-flop to form a scan chain),which will traverse to each node of the circuit.And At-speed test,that is,high-speed test,will use the OCC(on chip clock)circuit to generate the required high-speed clock.This is to test whether the DDR PHY can operate normally at the frequency it is designed to,and it can make the circuit capable Controllability and observability,circuit testing has changed from complicated to simplified,and the test accuracy and accuracy have been continuously improved.Finally,the test vector generated by the ATPG automatic test vector generation tool is used to achieve a stuck-at test failure coverage rate of 97.25%.Transition test The target coverage rate of 92.65% guarantees the yield rate of chips manufactured.(2)Test the correctness of the data transmission function of DDR PHY.Use APB(Advanced Peripheral Bus)and BIST(Built-In Self Test)built-in self-test technology to verify the DFT of the DDR PHY loopback function,load the test code control function register from the APB interface,and then start the internal BIST logic to Control the loopback path for data transmission.This is extremely effective for verifying the high transfer rate of DDR PHY analog and digital paths,and can also reduce test costs.Finally,the results are verified by simulation to ensure that the DDY PHY transceiver function is correct.(3)Carry out IOLT(input and output level)test.The input and output interface of DDR PHY is more complicated.In order to ensure that the I/O pins of the entire module can meet the requirements of DC specifications,the input and output tests are carried out by adopting a nand tree architecture specially used for auxiliary I/O parameter testing.To test all input and output pins and bidirectional pins to achieve IO parameter testing.And verify the result through simulation.The results of this paper have been applied to the wireless connection chip design,and the wireless connection chip is currently in the tape-out stage,so the research content on the one hand ensures that the DFT structure design of DDR PHY is reasonable,the data transmission function is normal,and the related engineering problems It also has reference significance.And negotiate with the back-end engineers to assist timing closure,final timing check,and post-simulation,as well as a series of sign-off checks,and finally to Tape-out.