Research On Test Data Compression Schemes For 3D-SoC

With the rapid development of the chip manufacturing industry,the manufacture of three-dimensional chips has gradually become possible.With the increase in chip integration,the amount of test data required for chip testing has increased.An increase in the amount of test data increases chip test time,test power consumption,and memory instruments required for testing,which results in increased chip test costs.Therefore,how to increase compression rate with lower test additional hardware overhead is the top priority of chip test research.This dissertation has carried out the following research on how to reduce the amount of test data of 3D IC:A dictionary-based test data compression scheme using tri-state coding is proposed.Firstly,the partial input reduction is used to improve the ratio of don't care bits in the test set to improve the success rate of the dictionary encoding.Then,a Tri-State detection circuit capable of detecting and identifying the Tri-State signal which ATE is utilized is used.Experimental results show that the average compression ratio of the proposed scheme reaches 73.92%.This scheme significantly improves the compression ratio with few hardware overhead,and is a feasible test data compression scheme.Finally,the decompression circuit of the scheme in the 3D IC test is proposed,which can be implemented in each layer of 3D IC,effectively reducing the problem of excessive test data in the three-dimensional chip test,so as to reduce the test cost.A reconfigurable built-in self-test scheme using a compatible compression algorithm is proposed.Based on the multi-polynomial re-seeding method of linear feedback shift register,this scheme proposes a built-in self-test structure suitable for pre-binding,binding and post-binding testing,and the test set compatible compression algorithm.Test data can be multiplexed in multiple layers for the purpose of reducing test application time.The experimental results compared with the non-reconfigurable schemes prove that this scheme has a good effect in reducing the area overhead,shortening the test time and reducing the amount of test data,which can reduce the test cost effectively.