Static Memory Test Methodology For 90nm Technology

Memory is one of the necessary parts of modern electronic system. On sort of storage characterization, it can be divided into such classes: Static RAM(SRAM); Dynamic RAM(DRAM); Programmable ROM(PROM); Erasable PROM(EPROM); Electrically Erasable PROM(EEPROM) and FlashMemory.Because of its characterization of high access speed and no needs of refreshing, SRAM is widely used in the field of high speed date process. Since IC industry follow with Moore's law [1], the bits of every chip are increasing exponentially. This will result to greater disturb between process and memory cell. With IC industry entering into submicron and deep submicron, we can not avoid process defect. If we don't have redundant cell, the yield of memory will be zero. Therefore, memory test and modifying the defect one is very important.In this paper, a detail analysis of Static RAM was done. The memory chip was tested using a new March algorithm. On the Teradyne J750 tester, function test, power test, chip logic test and date retention test were done in the environment of normal temperature, high and low temperature. Bit Fail Map (BFM) test was done to locate the fail memroy cell information, which is the key date of memory fault analysis and fault memory modification. In the way of analyzeing test result, some advices on the design were made.