Research And Implementation Of Dynamic Random Access Memory Test Pattern Algorithm Generation

Memory chips have a significant market share in the entire integrated circuit industry,with DRAM being a major component.As DRAM becomes more integrated and faster,the corresponding difficulty of DRAM test also increases.Due to the pattern-sensitive characteristics of memory storage arrays,DRAM test needs to be used in conjunction with test pattern algorithms.The efficiency and flexibility of test pattern algorithm generation directly affect the test time and results of memory chips test.Therefore,in order to ensure the effectiveness of memory chip test,the test pattern algorithm generation technology needs to be study.The traditional method of generating DRAM test pattern algorithms relies on manual writing of the pattern vectors,which is no longer applicable for today’s highly integrated high-speed memories.This method leads to low test efficiency and high test cost.Therefore,to address the problems of traditional test pattern algorithm generation efficiency,size and test cost,this thesis combines the design ideas of ATE tester and the memory built-in self-test(MBIST)circuit to study common faults of DRAM based on memory fault model.The thesis analyze the test pattern algorithms that cover these faults,and design a more flexible and efficient test algorithm pattern generator.Firstly,this thesis systematically studies the design requirements of the algorithm pattern generator.Combining the relevant theoretical basis of memory testing and existing implementation technologies,the thesis analyzes the functions and performance of the algorithm pattern generator,and carries out the overall scheme design of three submodules according to the divided main functions.At the same time,according to the requirements of the pin width and the number of test instructions of the memory chip under test,the performance index of the algorithm pattern generator is clarified,i.e.,the maximum storage depth of the memory array and the maximum number of achievable instructions are satisfied.Secondly,based on the design scheme,the design of the algorithm pattern generator is introduced in the form of block diagrams and state transition diagrams,and the circuit is described in Verilog hardware language in accordance with specific functions and modules.The algorithm pattern generator consists of three parts: instruction microprocessor,test pattern generation module and pin multiplexing module,and each module works together to generate the algorithm pattern vector that meets the requirements of the test sequence.Finally,the correctness of the generated algorithm pattern vector is verified by online debugging,and the oscilloscope pin signal waveform is acquired.The maximum storage depth of address signal is 24bits/24bits/8bits and the maximum storage depth of data signal is 32 bits.Taking DDR4 memory as an example,it is verified that the generated algorithmic pattern vector can realize the normal read/write operation of DDR4,which proves the expected requirement of the design.This thesis also discusses the shortcomings of the current design and proposes the next research direction.