Optimized Design Of 64bit GHz Integer Arithmetic And Logical Unit

As the technology is making progress rapidly in microelectronics, the feature size has reduced below 130nm, and the 65nm process has been in practical use. Thanks to the continuous improvement of integrated circuit technology, microprocessors are developing generation after generation, and the performance is improved rapidly. The speed of Arithmetic Logic Unit must be fast enough to design high performance microprocessors.In this thesis, a 64-bit GHz integer ALU is designed for steam processor X. A Semi-custom methodology based on standard cell is employed for the design of the main part, while the optimization of critical data-path is designed with a full-custom method. Without consuming too much time and labor, this design method improves the performance of the ALU from 500MHz to 1GHz, and it also solves the contradiction between large design scale and high performance in a better way. This 1GHz ALU design is practically applicable in a wide range of circumstance. This thesis mainly contributes to the following aspect:1 Optimization of the 64-bit 1GHz integer ALU, using a 130nm process, both the semi-custom and full-custom design parts meet with requirements. In typical case, delay of the semi-custom design parts is below 550ps. In full-custom parts, the layout of critical paths of 64-bit adder with static CMOS circuit have a delay of about 730ps, 270ps is the largest delay in the network of 64-bit funnel shifter which is constructed with static transmission gate arry.2 The high-speed logic design and optimization methodology is well studied, and some promotion are proposed in the design flow. Decision of logic levels, practical advices are brought out for circuit architecture chosen, parasitic feedback into tuning, full-custom design, and solutions for frequent problems in ALU design are presented. Finally, the optimization design methodology is made a practice in the optimization of 64-bit GHz integer ALU.3 A hierarchical full-custom design and verification methodology is well studied, which carry out the full-custom design and verification hierarchically in three aspects: design, optimization and verification. Static formal verification method was used to verify circuit function and RTL description. Static timing analysis after layout is used to help finding out the critical path in the design. The methodology improves the verification efficiency and speed up the full-custom design cycle.