Research On The Key Techniques Of DFT For Multi-core CPU

Recently, with the key techniques of multi-core processor becoming more mature, the market demand also keeps growing. Along with the shrinked process dimension, the chip integration is getting higher and higher, design complexity is also growing. Chip test and diagnosis of multi-core CPU become more and more important. In order to deal with the demand of test and fault diagnosis for large scale digital integrated circuit, design for testability(DFT) is proposed to increase the yield of products. DFT will add test logic to the function circuit without affecting the normal function of the chip, which can improve the testability of the chip and reduce the cost of testing chip. At present, many IC design companies are using DFT method in their design flow, so DFT has become a critical part of IC design flow.In this paper, after discussing about the basic principle, implementation method and the circuit structure of structured testability design techniques for multi-core CPU, we aimed at the problems and shortcomings of the current mainstream structured design method, some solutions are proposed based on the key techniques of design for testability for high performance multi-core CPU. And the logic verification have proved the effectiveness of these methods. In this paper, the main work and innovation points are summarized as follows:(1) A hybrid scan design method is proposed based on hierarchical and fault isolation design conception to solve the problem of the testing equipment limitation for current scan design with only relies on EDT( Embedded Deterministic Test). This method achieved self-test on the board level and aging test for chip products by combining compressed scan chain logic and logic built in-self test( Ligic BIST) for scan chain design of very large scale multi-core CPU.(2) Based on the traditional memory built-in self-test technique, at-speed BIST hierarchical design method of embedded memory based on the shared bus is proposed for fault detection requirements of embedded memory in the multi-core CPU, which reduces the timing influence on the critical path for the selection logic in the input port of memory in the traditional MBIST circuit.(3) In order to meet the multi-core CPU I/O PAD's fault detection requirement, research on boundary scan chain design for the FX chip is conducted on the base of the logic vision design flow. The method simplified the design flow, accomplished the test for the boundary I/O pin around the chip and the board level inter-connect.This paper proposed new design methods about three kinds of structured design methods, accomplised circuit designing and the functional result is correct, which demonstrated the feasibility and effectiveness of the methods.