Fpga Containing The Macro Module Generation And Processing Sequence Of Numbers To Match The Logical Unit Mapping Algorithm

A complete FPGA design flow includes FPGA hardware architecture design and the corresponding software system design.A specialized software system should be provided for each different FPGA chip.As the structure of FPGA logic block varies, it is likely that for each newly produced FPGA chip, the logic block mapping module needs to be re-programmed, which brings inconveniency for both research and production.A recently introduced logic block mapping algorithm FDUMAP claims its universal application to different FPGAs, but as the types and number of the FPGA components increase, FDUMAP shows it weakness in running time.This thesis's work is mainly about the logic block mapping module of the FPGA software system.Common features of modern mainstream FPGAs'logic blocks are listed in this thesis.According to these common features, a logic block mapping algorithm NSM is introduced.NSM converts circuits into a series of numerical sequences and then complete the mapping procedure by matching the numerical sequences of the logic block and the user's input circuit. NSM can be applied to many mainstream FPGAs such as Xilinx Spartan family and Virtex family FPGAs.The rules of converting a circuit into numerical sequences are not strictly fixed. If new types of components appear in logic block, or the structure of the logic block changes, minute adjustment can be applied on NSM to meet the needs of the new logic block. The running time of NSM is O(n2), which is far less than the O(nm) complexity of the original matching algorithm of logic block mapping, where n is the number of components in user's input circuit and m is the average number of components of a functional circuit in an FPGA's logic block.Other than the optimization on complexity, NSM also consider the area saving and universal application of mapping algorithm.The test result shows that NSM has fine results in both aspects.Based on NSM, a flexible packing tool FlexPack is also introduced in this thesis.FlexPack allows "Macro Block" mapping, which combines a definable number of logic blocks into a "Macro Block", and then use this block as the object of mapping. FlexPack introduces generation of "Macro Block" in mapping for the first time.The test results shows that FlexPack has fine results on user's input circuits of medium and small scales.