Design Of Radar Timer Based On FPGA Local Dynamic Reconfiguration Technology

In the radar system, the radar timer is a very critical component. Today, with the rapid development of digital signal processing technology, the radar timer is also widespread use of digital signal processing technology. But field-programmable gate array(FPGA) is widely used in radar timer so that FPGA in radar timer generates the timing signal also occupies an important position.In this field,to use reconfigurable gate array features an editable FPGA can develop high stability and safety factor electronic products in short time.To make dynamic partial reconfigurable FPGA technology for the design of radar timer, not only to improve the stability of the output pulse radar timer design and shorten the development cycle, but also to ensure the system to be safe and reliable, while to make the hardware has configurability.This paper make to focus onusing of dynamic partial reconfigurable FPGA design implementation timer radar design, the main work includes: in-depth study of the theory and FPGA design flow to explore the dynamic reconfiguration system design, and in-depth analysis of radar timer operation principle, proposed a simplified dynamic self-reconfigurable system design. Being based on the use of the early part of the reconfiguration process and the principles of design, dynamic reconfiguration logic level on the basis of already existing, to further simplify the original design process, dynamic local self-reconfigurable. With examples of the proposed design method it will be used in radar timer design, dynamic reconfiguration error by assuming that the module, create a reliable, modular and dynamic partial reconfigurable system, prove feasibility and superiority of the proposed method.The research mainly from the following several aspects:(1) in this paper, first of all, the research and discusses the local dynamic reconfiguration technology in radar timer on the use of the background and significance;(2) based on FPGA as the main research object, and based on the FPGA design process of SRAM, basic structure, logical structure, dynamic reconstruction principle and data configuration process is studied.(3) finally, the local dynamic reconfiguration technology of radar timer based on FPGA, and completed the framework of design scheme. Under the design scheme, the partial to refactor the layout, the time slot in the process of control are studied, put forward the solution.This topic research for reconstructing the FPGA technology in the fault tolerance technology, radar signal processing, data analysis, the application of radar wave velocity scheduling schemes such as lay a certain foundation, have certain reference value.