Study Of Dynamic Reconfiguration Of FPGA

With the development of microelectronics and computer technologies, RTR is becoming a new hotspot in the field of the computer system research. It makes the boundary of hardware and software to be confused and makes the hardware system to become software. The dynamic reconfiguration of FPGA has two main styles: Module-based and Difference-based partial reconfiguration. The method of difference-based partial reconfiguration is accomplished by making a small change to the circuit design, and then generates a bitstream only including the differences in the fore-and-aft reconfiguration designs. If the designs consist of large blocks of logic, and the function is very complex, the Module-based partial reconfiguration is required. The project uses the Module-based partial reconfiguration.It can create the bitstreams of the whole circuit and the dynamic partial reconfiguration by the top-level design synthesis, modules synthesis, initial budgeting, active module implementation and final assembly. The bitstreams are separately downloaded to Virtex2-Pro ML310 and rationally controlled the time sequence by the interior controller, and then realizes the dynamic reconfiguration, the result can be observed from the experiment board. Base on the analysis of the result, we can get that the size of the file using normal method is 5.82 times to the file using partial reconfiguration, the download speed using the partial reconfiguration is greatly improved, and it reflects the advantage of partial reconfiguration. With the increase of the circuit complexity, the partial reconfiguration can realize the whole function of biggish time sequence system by using less hardware resource. Thus, the utilization ratio of the board is increasing, and the advantage of partial reconfiguration is becoming more obvious...